1. Field of the Invention
The invention relates generally to integrated circuit manufacturing, and more particularly to interconnection structures that include the substrate of an integrated circuit and methods for making the same.
2. Background
Advances in semiconductor process technology and digital system architecture have led to integrated circuits having increased operating frequencies. Higher operating frequencies typically result in undesirable increases in power consumption. Power consumption is a significant problem for integrated circuits (ICs) generally, and particularly for large scale, complex, high speed products such as processors and microprocessors.
Nonetheless, the trend of integrating more functions on a single chip, while operating at ever higher frequencies goes on unabated.
One well-known way to reduce power consumption is by reducing the power supply voltage used by integrated circuits. Unfortunately, reduced operating voltages result in design constraints with respect to noise margin, and require greater care, and typically more area, in the layout of power distribution lines. More area is typically required for widening of the power distribution lines in order to reduce resistance and thus reduce undesirable voltage drops.
What is needed is an interconnect structure for integrated circuits that reduces the noise margin and voltage drop constraints commonly found in integrated circuits having low power supply voltages. What is further needed is a method of manufacturing such a structure.
Briefly, a backside interconnect structure is used to deliver power through the substrate to the front side of an integrated circuit.
In a specific embodiment of the present invention, power planes are formed on the back side of a substrate, and a series of deep vias through the substrate are used to couple the power planes to front side metal lines, and to well taps.